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4.18.0-553.63.1.el8_10.x86_64
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include
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sound
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UPLOAD:
NAME
SIZE
QUICK PERMS
ACTIONS
📁 ac97
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📁 sof
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📄 ac97_codec.h
16,173 B
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📄 aci.h
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📄 acp63_chip_offset_byte.h
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📄 ad1816a.h
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📄 ad1843.h
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📄 adau1373.h
706 B
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📄 aess.h
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📄 ak4113.h
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📄 ak4114.h
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📄 ak4117.h
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📄 ak4531_codec.h
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📄 ak4641.h
476 B
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📄 ak4xxx-adda.h
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📄 alc5623.h
536 B
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📄 asequencer.h
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📄 asound.h
590 B
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📄 asoundef.h
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📄 compress_driver.h
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📄 control.h
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📄 core.h
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📄 cs35l33.h
888 B
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📄 cs35l34.h
741 B
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📄 cs35l35.h
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📄 cs35l36.h
772 B
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📄 cs35l41.h
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📄 cs4231-regs.h
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📄 cs4271.h
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📄 cs42l42.h
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📄 cs42l52.h
592 B
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📄 cs42l56.h
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📄 cs42l73.h
361 B
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📄 cs8403.h
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📄 cs8427.h
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📄 da7213.h
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📄 da7218.h
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📄 da7219-aad.h
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📄 da7219.h
998 B
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📄 da9055.h
707 B
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📄 designware_i2s.h
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📄 dmaengine_pcm.h
6,802 B
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📄 emu10k1.h
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📄 emu10k1_synth.h
693 B
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📄 emu8000.h
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📄 emu8000_reg.h
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📄 emux_legacy.h
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📄 emux_synth.h
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📄 es1688.h
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📄 graph_card.h
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📄 gus.h
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📄 hda-mlink.h
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📄 hda_chmap.h
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📄 hda_codec.h
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📄 hda_component.h
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📄 hda_hwdep.h
736 B
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📄 hda_i915.h
589 B
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📄 hda_register.h
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📄 hda_regmap.h
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📄 hda_verbs.h
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📄 hdaudio.h
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📄 hdaudio_ext.h
6,626 B
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📄 hdmi-codec.h
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📄 hwdep.h
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📄 i2c.h
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📄 info.h
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📄 initval.h
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📄 intel-dsp-config.h
896 B
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📄 intel-nhlt.h
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📄 jack.h
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📄 l3.h
524 B
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📄 max9768.h
729 B
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📄 max98088.h
1,074 B
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📄 max98090.h
534 B
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📄 max98095.h
1,357 B
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📄 memalloc.h
3,879 B
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📄 minors.h
3,738 B
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📄 mixer_oss.h
1,773 B
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📄 mpu401.h
3,905 B
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📄 omap-hdmi-audio.h
971 B
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📄 opl3.h
11,909 B
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📄 opl4.h
459 B
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📄 pcm-indirect.h
5,303 B
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📄 pcm.h
55,007 B
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📄 pcm_drm_eld.h
183 B
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📄 pcm_iec958.h
597 B
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📄 pcm_oss.h
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📄 pcm_params.h
8,864 B
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📄 pt2258.h
513 B
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📄 pxa2xx-lib.h
2,190 B
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📄 rawmidi.h
5,663 B
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📄 rt1015.h
283 B
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📄 rt286.h
314 B
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📄 rt298.h
373 B
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📄 rt5514.h
399 B
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📄 rt5659.h
880 B
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📄 rt5660.h
578 B
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📄 rt5663.h
476 B
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📄 rt5665.h
723 B
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📄 rt5668.h
607 B
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📄 rt5682.h
862 B
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📄 rt5682s.h
915 B
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📄 s3c24xx_uda134x.h
229 B
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📄 sb.h
10,550 B
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📄 sb16_csp.h
2,100 B
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📄 sdw.h
1,667 B
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📄 seq_device.h
2,165 B
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📄 seq_kernel.h
3,378 B
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📄 seq_midi_emul.h
6,757 B
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📄 seq_midi_event.h
1,356 B
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📄 seq_oss.h
2,264 B
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📄 seq_oss_legacy.h
360 B
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📄 seq_virmidi.h
2,123 B
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📄 sh_dac_audio.h
441 B
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📄 sh_fsi.h
693 B
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📄 simple_card.h
529 B
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📄 simple_card_utils.h
8,816 B
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📄 snd_wavefront.h
5,704 B
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📄 soc-acpi-intel-match.h
2,417 B
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📄 soc-acpi.h
6,675 B
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📄 soc-card.h
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📄 soc-component.h
20,608 B
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📄 soc-dai.h
21,113 B
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📄 soc-dapm.h
34,141 B
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📄 soc-dpcm.h
5,698 B
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📄 soc-jack.h
3,822 B
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📄 soc-link.h
1,172 B
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📄 soc-topology.h
5,882 B
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📄 soc.h
52,841 B
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📄 sof.h
4,031 B
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📄 soundfont.h
3,903 B
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📄 spear_dma.h
350 B
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📄 spear_spdif.h
345 B
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📄 sta32x.h
1,015 B
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📄 sta350.h
1,474 B
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📄 tas2552-plat.h
283 B
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📄 tas5086.h
210 B
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📄 tea6330t.h
468 B
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📄 timer.h
5,125 B
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📄 tlv.h
1,627 B
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📄 tlv320aic32x4.h
1,320 B
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📄 tlv320dac33-plat.h
574 B
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📄 tpa6130a2-plat.h
291 B
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📄 uda134x.h
451 B
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📄 uda1380.h
335 B
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📄 util_mem.h
1,623 B
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📄 vx_core.h
15,055 B
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📄 wavefront.h
18,518 B
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📄 wm0010.h
466 B
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📄 wm1250-ev1.h
510 B
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📄 wm2000.h
479 B
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📄 wm2200.h
1,353 B
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📄 wm5100.h
1,129 B
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📄 wm8903.h
15,377 B
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📄 wm8904.h
7,389 B
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📄 wm8955.h
442 B
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📄 wm8960.h
888 B
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📄 wm8962.h
1,694 B
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📄 wm8993.h
1,076 B
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📄 wm8996.h
1,289 B
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📄 wm9081.h
515 B
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📄 wm9090.h
634 B
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📄 wss.h
7,949 B
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EDIT: wm8903.h
/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/sound/wm8903.h -- Platform data for WM8903 * * Copyright 2010 Wolfson Microelectronics. PLC. */ #ifndef __LINUX_SND_WM8903_H #define __LINUX_SND_WM8903_H /* * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of * zero in platform data means "don't touch this pin". */ #define WM8903_GPIO_CONFIG_ZERO 0x8000 /* * R6 (0x06) - Mic Bias Control 0 */ #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */ #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */ #define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */ #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ /* * WM8903_GPn_FN values * * See datasheets for list of valid values per pin */ #define WM8903_GPn_FN_GPIO_OUTPUT 0 #define WM8903_GPn_FN_BCLK 1 #define WM8903_GPn_FN_IRQ_OUTPT 2 #define WM8903_GPn_FN_GPIO_INPUT 3 #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4 #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5 #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6 #define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8 #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9 /* * R116 (0x74) - GPIO Control 1 */ #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ #define WM8903_GP1_PD 0x0008 /* GP1_PD */ #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ #define WM8903_GP1_PU 0x0004 /* GP1_PU */ #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ #define WM8903_GP1_DB 0x0001 /* GP1_DB */ #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ /* * R117 (0x75) - GPIO Control 2 */ #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ #define WM8903_GP2_PD 0x0008 /* GP2_PD */ #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ #define WM8903_GP2_PU 0x0004 /* GP2_PU */ #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ #define WM8903_GP2_DB 0x0001 /* GP2_DB */ #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ /* * R118 (0x76) - GPIO Control 3 */ #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ #define WM8903_GP3_PD 0x0008 /* GP3_PD */ #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ #define WM8903_GP3_PU 0x0004 /* GP3_PU */ #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ #define WM8903_GP3_DB 0x0001 /* GP3_DB */ #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ /* * R119 (0x77) - GPIO Control 4 */ #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ #define WM8903_GP4_PD 0x0008 /* GP4_PD */ #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ #define WM8903_GP4_PU 0x0004 /* GP4_PU */ #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ #define WM8903_GP4_DB 0x0001 /* GP4_DB */ #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ /* * R120 (0x78) - GPIO Control 5 */ #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ #define WM8903_GP5_PD 0x0008 /* GP5_PD */ #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ #define WM8903_GP5_PU 0x0004 /* GP5_PU */ #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ #define WM8903_GP5_DB 0x0001 /* GP5_DB */ #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ #define WM8903_NUM_GPIO 5 struct wm8903_platform_data { bool irq_active_low; /* Set if IRQ active low, default high */ /* Default register value for R6 (Mic bias), used to configure * microphone detection. In conjunction with gpio_cfg this * can be used to route the microphone status signals out onto * the GPIOs for use with snd_soc_jack_add_gpios(). */ u16 micdet_cfg; int micdet_delay; /* Delay after microphone detection (ms) */ int gpio_base; u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */ }; #endif