[ SYSTEM ]: Linux srv.persadacompanies.com 4.18.0-553.56.1.el8_10.x86_64 #1 SMP Tue Jun 10 05:00:59 EDT 2025 x86_64
[ SERVER ]: Apache | PHP: 8.4.19
[ USER ]: persadamedika | IP: 45.64.1.108
GEFORCE FILE MANAGER
/
usr
/
src
/
kernels
/
4.18.0-553.64.1.el8_10.x86_64
/
include
/
uapi
/
linux
/
UPLOAD:
NAME
SIZE
QUICK PERMS
ACTIONS
📁 android
SET
[ DEL ]
📁 byteorder
SET
[ DEL ]
📁 caif
SET
[ DEL ]
📁 can
SET
[ DEL ]
📁 cifs
SET
[ DEL ]
📁 dvb
SET
[ DEL ]
📁 genwqe
SET
[ DEL ]
📁 hdlc
SET
[ DEL ]
📁 hsi
SET
[ DEL ]
📁 iio
SET
[ DEL ]
📁 isdn
SET
[ DEL ]
📁 mmc
SET
[ DEL ]
📁 netfilter
SET
[ DEL ]
📁 netfilter_arp
SET
[ DEL ]
📁 netfilter_bridge
SET
[ DEL ]
📁 netfilter_ipv4
SET
[ DEL ]
📁 netfilter_ipv6
SET
[ DEL ]
📁 nfsd
SET
[ DEL ]
📁 raid
SET
[ DEL ]
📁 sched
SET
[ DEL ]
📁 spi
SET
[ DEL ]
📁 sunrpc
SET
[ DEL ]
📁 tc_act
SET
[ DEL ]
📁 tc_ematch
SET
[ DEL ]
📁 usb
SET
[ DEL ]
📁 wimax
SET
[ DEL ]
📄 Kbuild
352 B
SET
[ EDIT ]
|
[ DEL ]
📄 a.out.h
6,959 B
SET
[ EDIT ]
|
[ DEL ]
📄 acct.h
3,915 B
SET
[ EDIT ]
|
[ DEL ]
📄 adb.h
1,155 B
SET
[ EDIT ]
|
[ DEL ]
📄 adfs_fs.h
951 B
SET
[ EDIT ]
|
[ DEL ]
📄 affs_hardblocks.h
1,544 B
SET
[ EDIT ]
|
[ DEL ]
📄 agpgart.h
4,001 B
SET
[ EDIT ]
|
[ DEL ]
📄 aio_abi.h
3,417 B
SET
[ EDIT ]
|
[ DEL ]
📄 am437x-vpfe.h
3,681 B
SET
[ EDIT ]
|
[ DEL ]
📄 apm_bios.h
3,698 B
SET
[ EDIT ]
|
[ DEL ]
📄 arcfb.h
213 B
SET
[ EDIT ]
|
[ DEL ]
📄 arm_sdei.h
2,766 B
SET
[ EDIT ]
|
[ DEL ]
📄 aspeed-lpc-ctrl.h
1,795 B
SET
[ EDIT ]
|
[ DEL ]
📄 atalk.h
1,038 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm.h
7,937 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_eni.h
648 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_he.h
406 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_idt77105.h
955 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_nicstar.h
1,278 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_tcp.h
1,637 B
SET
[ EDIT ]
|
[ DEL ]
📄 atm_zatm.h
1,540 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmapi.h
952 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmarp.h
1,296 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmbr2684.h
3,271 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmclip.h
576 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmdev.h
7,699 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmioc.h
1,646 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmlec.h
2,381 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmmpc.h
4,226 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmppp.h
639 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmsap.h
4,970 B
SET
[ EDIT ]
|
[ DEL ]
📄 atmsvc.h
1,853 B
SET
[ EDIT ]
|
[ DEL ]
📄 audit.h
20,409 B
SET
[ EDIT ]
|
[ DEL ]
📄 auto_dev-ioctl.h
4,997 B
SET
[ EDIT ]
|
[ DEL ]
📄 auto_fs.h
6,450 B
SET
[ EDIT ]
|
[ DEL ]
📄 auto_fs4.h
466 B
SET
[ EDIT ]
|
[ DEL ]
📄 auxvec.h
1,612 B
SET
[ EDIT ]
|
[ DEL ]
📄 ax25.h
2,824 B
SET
[ EDIT ]
|
[ DEL ]
📄 b1lli.h
1,717 B
SET
[ EDIT ]
|
[ DEL ]
📄 batadv_packet.h
20,510 B
SET
[ EDIT ]
|
[ DEL ]
📄 batman_adv.h
11,992 B
SET
[ EDIT ]
|
[ DEL ]
📄 baycom.h
883 B
SET
[ EDIT ]
|
[ DEL ]
📄 bcache.h
8,306 B
SET
[ EDIT ]
|
[ DEL ]
📄 bcm933xx_hcs.h
419 B
SET
[ EDIT ]
|
[ DEL ]
📄 bfs_fs.h
1,893 B
SET
[ EDIT ]
|
[ DEL ]
📄 binfmts.h
643 B
SET
[ EDIT ]
|
[ DEL ]
📄 blkpg.h
953 B
SET
[ EDIT ]
|
[ DEL ]
📄 blktrace_api.h
4,716 B
SET
[ EDIT ]
|
[ DEL ]
📄 blkzoned.h
6,623 B
SET
[ EDIT ]
|
[ DEL ]
📄 bpf.h
228,675 B
SET
[ EDIT ]
|
[ DEL ]
📄 bpf_common.h
1,382 B
SET
[ EDIT ]
|
[ DEL ]
📄 bpf_perf_event.h
544 B
SET
[ EDIT ]
|
[ DEL ]
📄 bpfilter.h
480 B
SET
[ EDIT ]
|
[ DEL ]
📄 bpqether.h
981 B
SET
[ EDIT ]
|
[ DEL ]
📄 bsg.h
2,509 B
SET
[ EDIT ]
|
[ DEL ]
📄 bt-bmc.h
587 B
SET
[ EDIT ]
|
[ DEL ]
📄 btf.h
4,811 B
SET
[ EDIT ]
|
[ DEL ]
📄 btrfs.h
28,942 B
SET
[ EDIT ]
|
[ DEL ]
📄 btrfs_tree.h
25,265 B
SET
[ EDIT ]
|
[ DEL ]
📄 can.h
7,891 B
SET
[ EDIT ]
|
[ DEL ]
📄 capability.h
13,576 B
SET
[ EDIT ]
|
[ DEL ]
📄 capi.h
3,157 B
SET
[ EDIT ]
|
[ DEL ]
📄 cciss_defs.h
3,281 B
SET
[ EDIT ]
|
[ DEL ]
📄 cciss_ioctl.h
2,790 B
SET
[ EDIT ]
|
[ DEL ]
📄 cdrom.h
28,902 B
SET
[ EDIT ]
|
[ DEL ]
📄 cec-funcs.h
53,293 B
SET
[ EDIT ]
|
[ DEL ]
📄 cec.h
37,611 B
SET
[ EDIT ]
|
[ DEL ]
📄 cfm_bridge.h
1,466 B
SET
[ EDIT ]
|
[ DEL ]
📄 cgroupstats.h
2,219 B
SET
[ EDIT ]
|
[ DEL ]
📄 chio.h
5,351 B
SET
[ EDIT ]
|
[ DEL ]
📄 close_range.h
392 B
SET
[ EDIT ]
|
[ DEL ]
📄 cm4000_cs.h
1,821 B
SET
[ EDIT ]
|
[ DEL ]
📄 cn_proc.h
3,471 B
SET
[ EDIT ]
|
[ DEL ]
📄 coda.h
17,682 B
SET
[ EDIT ]
|
[ DEL ]
📄 coda_psdev.h
798 B
SET
[ EDIT ]
|
[ DEL ]
📄 coff.h
12,476 B
SET
[ EDIT ]
|
[ DEL ]
📄 connector.h
2,268 B
SET
[ EDIT ]
|
[ DEL ]
📄 const.h
803 B
SET
[ EDIT ]
|
[ DEL ]
📄 coresight-stm.h
674 B
SET
[ EDIT ]
|
[ DEL ]
📄 cramfs_fs.h
3,570 B
SET
[ EDIT ]
|
[ DEL ]
📄 cryptouser.h
3,392 B
SET
[ EDIT ]
|
[ DEL ]
📄 cuda.h
920 B
SET
[ EDIT ]
|
[ DEL ]
📄 cyclades.h
17,123 B
SET
[ EDIT ]
|
[ DEL ]
📄 cycx_cfm.h
2,990 B
SET
[ EDIT ]
|
[ DEL ]
📄 dcbnl.h
25,238 B
SET
[ EDIT ]
|
[ DEL ]
📄 dccp.h
6,447 B
SET
[ EDIT ]
|
[ DEL ]
📄 devlink.h
21,571 B
SET
[ EDIT ]
|
[ DEL ]
📄 dlm.h
2,568 B
SET
[ EDIT ]
|
[ DEL ]
📄 dlm_device.h
2,599 B
SET
[ EDIT ]
|
[ DEL ]
📄 dlm_netlink.h
1,159 B
SET
[ EDIT ]
|
[ DEL ]
📄 dlm_plock.h
909 B
SET
[ EDIT ]
|
[ DEL ]
📄 dlmconstants.h
5,080 B
SET
[ EDIT ]
|
[ DEL ]
📄 dm-ioctl.h
11,400 B
SET
[ EDIT ]
|
[ DEL ]
📄 dm-log-userspace.h
15,191 B
SET
[ EDIT ]
|
[ DEL ]
📄 dma-buf.h
5,247 B
SET
[ EDIT ]
|
[ DEL ]
📄 dn.h
4,642 B
SET
[ EDIT ]
|
[ DEL ]
📄 dqblk_xfs.h
9,245 B
SET
[ EDIT ]
|
[ DEL ]
📄 edd.h
5,619 B
SET
[ EDIT ]
|
[ DEL ]
📄 efs_fs_sb.h
2,227 B
SET
[ EDIT ]
|
[ DEL ]
📄 elf-em.h
2,187 B
SET
[ EDIT ]
|
[ DEL ]
📄 elf-fdpic.h
1,139 B
SET
[ EDIT ]
|
[ DEL ]
📄 elf.h
13,486 B
SET
[ EDIT ]
|
[ DEL ]
📄 elfcore.h
3,062 B
SET
[ EDIT ]
|
[ DEL ]
📄 errno.h
23 B
SET
[ EDIT ]
|
[ DEL ]
📄 errqueue.h
1,492 B
SET
[ EDIT ]
|
[ DEL ]
📄 erspan.h
1,074 B
SET
[ EDIT ]
|
[ DEL ]
📄 ethtool.h
83,872 B
SET
[ EDIT ]
|
[ DEL ]
📄 ethtool_netlink.h
22,841 B
SET
[ EDIT ]
|
[ DEL ]
📄 eventpoll.h
2,869 B
SET
[ EDIT ]
|
[ DEL ]
📄 fadvise.h
842 B
SET
[ EDIT ]
|
[ DEL ]
📄 falloc.h
3,599 B
SET
[ EDIT ]
|
[ DEL ]
📄 fanotify.h
5,356 B
SET
[ EDIT ]
|
[ DEL ]
📄 fb.h
16,518 B
SET
[ EDIT ]
|
[ DEL ]
📄 fcntl.h
4,189 B
SET
[ EDIT ]
|
[ DEL ]
📄 fd.h
11,721 B
SET
[ EDIT ]
|
[ DEL ]
📄 fdreg.h
5,420 B
SET
[ EDIT ]
|
[ DEL ]
📄 fib_rules.h
2,036 B
SET
[ EDIT ]
|
[ DEL ]
📄 fiemap.h
2,775 B
SET
[ EDIT ]
|
[ DEL ]
📄 filter.h
2,265 B
SET
[ EDIT ]
|
[ DEL ]
📄 firewire-cdev.h
43,886 B
SET
[ EDIT ]
|
[ DEL ]
📄 firewire-constants.h
3,231 B
SET
[ EDIT ]
|
[ DEL ]
📄 flat.h
2,163 B
SET
[ EDIT ]
|
[ DEL ]
📄 fou.h
709 B
SET
[ EDIT ]
|
[ DEL ]
📄 fpga-dfl.h
8,743 B
SET
[ EDIT ]
|
[ DEL ]
📄 fs.h
13,511 B
SET
[ EDIT ]
|
[ DEL ]
📄 fsl_hypervisor.h
7,316 B
SET
[ EDIT ]
|
[ DEL ]
📄 fsmap.h
4,385 B
SET
[ EDIT ]
|
[ DEL ]
📄 fuse.h
23,529 B
SET
[ EDIT ]
|
[ DEL ]
📄 futex.h
5,049 B
SET
[ EDIT ]
|
[ DEL ]
📄 gameport.h
912 B
SET
[ EDIT ]
|
[ DEL ]
📄 gen_stats.h
1,526 B
SET
[ EDIT ]
|
[ DEL ]
📄 genetlink.h
2,190 B
SET
[ EDIT ]
|
[ DEL ]
📄 gfs2_ondisk.h
14,739 B
SET
[ EDIT ]
|
[ DEL ]
📄 gigaset_dev.h
1,442 B
SET
[ EDIT ]
|
[ DEL ]
📄 gpio.h
6,766 B
SET
[ EDIT ]
|
[ DEL ]
📄 gsmmux.h
1,041 B
SET
[ EDIT ]
|
[ DEL ]
📄 gtp.h
696 B
SET
[ EDIT ]
|
[ DEL ]
📄 hash_info.h
936 B
SET
[ EDIT ]
|
[ DEL ]
📄 hdlc.h
652 B
SET
[ EDIT ]
|
[ DEL ]
📄 hdlcdrv.h
2,923 B
SET
[ EDIT ]
|
[ DEL ]
📄 hdreg.h
22,945 B
SET
[ EDIT ]
|
[ DEL ]
📄 hid.h
1,916 B
SET
[ EDIT ]
|
[ DEL ]
📄 hiddev.h
6,360 B
SET
[ EDIT ]
|
[ DEL ]
📄 hidraw.h
2,008 B
SET
[ EDIT ]
|
[ DEL ]
📄 hpet.h
785 B
SET
[ EDIT ]
|
[ DEL ]
📄 hsr_netlink.h
1,081 B
SET
[ EDIT ]
|
[ DEL ]
📄 hw_breakpoint.h
757 B
SET
[ EDIT ]
|
[ DEL ]
📄 hyperv.h
11,167 B
SET
[ EDIT ]
|
[ DEL ]
📄 hysdn_if.h
1,382 B
SET
[ EDIT ]
|
[ DEL ]
📄 i2c-dev.h
2,668 B
SET
[ EDIT ]
|
[ DEL ]
📄 i2c.h
7,147 B
SET
[ EDIT ]
|
[ DEL ]
📄 i2o-dev.h
11,646 B
SET
[ EDIT ]
|
[ DEL ]
📄 i8k.h
1,528 B
SET
[ EDIT ]
|
[ DEL ]
📄 icmp.h
2,990 B
SET
[ EDIT ]
|
[ DEL ]
📄 icmpv6.h
4,053 B
SET
[ EDIT ]
|
[ DEL ]
📄 idxd.h
8,461 B
SET
[ EDIT ]
|
[ DEL ]
📄 if.h
10,984 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_addr.h
1,912 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_addrlabel.h
721 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_alg.h
946 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_arcnet.h
3,717 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_arp.h
6,592 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_bonding.h
5,291 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_bridge.h
19,529 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_cablemodem.h
986 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_eql.h
1,364 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_ether.h
8,263 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_fc.h
1,738 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_fddi.h
3,763 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_frad.h
3,034 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_hippi.h
4,235 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_infiniband.h
1,245 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_link.h
31,698 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_ltalk.h
225 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_macsec.h
5,847 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_packet.h
7,919 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_phonet.h
439 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_plip.h
660 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_ppp.h
29 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_pppol2tp.h
3,307 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_pppox.h
4,804 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_slip.h
872 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_team.h
2,615 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_tun.h
4,113 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_tunnel.h
4,535 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_vlan.h
1,846 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_x25.h
881 B
SET
[ EDIT ]
|
[ DEL ]
📄 if_xdp.h
3,011 B
SET
[ EDIT ]
|
[ DEL ]
📄 ife.h
351 B
SET
[ EDIT ]
|
[ DEL ]
📄 igmp.h
3,079 B
SET
[ EDIT ]
|
[ DEL ]
📄 ila.h
1,261 B
SET
[ EDIT ]
|
[ DEL ]
📄 in.h
10,137 B
SET
[ EDIT ]
|
[ DEL ]
📄 in6.h
7,453 B
SET
[ EDIT ]
|
[ DEL ]
📄 in_route.h
936 B
SET
[ EDIT ]
|
[ DEL ]
📄 inet_diag.h
4,687 B
SET
[ EDIT ]
|
[ DEL ]
📄 inotify.h
3,307 B
SET
[ EDIT ]
|
[ DEL ]
📄 input-event-codes.h
28,616 B
SET
[ EDIT ]
|
[ DEL ]
📄 input.h
16,033 B
SET
[ EDIT ]
|
[ DEL ]
📄 io_uring.h
6,207 B
SET
[ EDIT ]
|
[ DEL ]
📄 ioctl.h
163 B
SET
[ EDIT ]
|
[ DEL ]
📄 iommu.h
4,919 B
SET
[ EDIT ]
|
[ DEL ]
📄 ip.h
4,826 B
SET
[ EDIT ]
|
[ DEL ]
📄 ip6_tunnel.h
1,953 B
SET
[ EDIT ]
|
[ DEL ]
📄 ip_vs.h
13,631 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipc.h
2,123 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipmi.h
15,505 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipmi_bmc.h
479 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipmi_msgdefs.h
3,430 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipmi_ssif_bmc.h
456 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipsec.h
947 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipv6.h
3,982 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipv6_route.h
1,923 B
SET
[ EDIT ]
|
[ DEL ]
📄 ipx.h
2,347 B
SET
[ EDIT ]
|
[ DEL ]
📄 irqnr.h
104 B
SET
[ EDIT ]
|
[ DEL ]
📄 isdn.h
5,789 B
SET
[ EDIT ]
|
[ DEL ]
📄 isdn_divertif.h
1,215 B
SET
[ EDIT ]
|
[ DEL ]
📄 isdn_ppp.h
1,938 B
SET
[ EDIT ]
|
[ DEL ]
📄 isdnif.h
2,385 B
SET
[ EDIT ]
|
[ DEL ]
📄 iso_fs.h
6,485 B
SET
[ EDIT ]
|
[ DEL ]
📄 isst_if.h
5,384 B
SET
[ EDIT ]
|
[ DEL ]
📄 ivtv.h
3,063 B
SET
[ EDIT ]
|
[ DEL ]
📄 ivtvfb.h
1,241 B
SET
[ EDIT ]
|
[ DEL ]
📄 jffs2.h
7,018 B
SET
[ EDIT ]
|
[ DEL ]
📄 joystick.h
3,449 B
SET
[ EDIT ]
|
[ DEL ]
📄 kcm.h
822 B
SET
[ EDIT ]
|
[ DEL ]
📄 kcmp.h
537 B
SET
[ EDIT ]
|
[ DEL ]
📄 kcov.h
1,099 B
SET
[ EDIT ]
|
[ DEL ]
📄 kd.h
6,316 B
SET
[ EDIT ]
|
[ DEL ]
📄 kdev_t.h
441 B
SET
[ EDIT ]
|
[ DEL ]
📄 kernel-page-flags.h
915 B
SET
[ EDIT ]
|
[ DEL ]
📄 kernel.h
453 B
SET
[ EDIT ]
|
[ DEL ]
📄 kernelcapi.h
1,034 B
SET
[ EDIT ]
|
[ DEL ]
📄 kexec.h
1,893 B
SET
[ EDIT ]
|
[ DEL ]
📄 keyboard.h
12,798 B
SET
[ EDIT ]
|
[ DEL ]
📄 keyctl.h
3,514 B
SET
[ EDIT ]
|
[ DEL ]
📄 kfd_ioctl.h
28,814 B
SET
[ EDIT ]
|
[ DEL ]
📄 kfd_sysfs.h
4,350 B
SET
[ EDIT ]
|
[ DEL ]
📄 kvm.h
61,602 B
SET
[ EDIT ]
|
[ DEL ]
📄 kvm_para.h
1,016 B
SET
[ EDIT ]
|
[ DEL ]
📄 l2tp.h
5,606 B
SET
[ EDIT ]
|
[ DEL ]
📄 libc-compat.h
8,304 B
SET
[ EDIT ]
|
[ DEL ]
📄 lightnvm.h
5,168 B
SET
[ EDIT ]
|
[ DEL ]
📄 limits.h
947 B
SET
[ EDIT ]
|
[ DEL ]
📄 lirc.h
7,813 B
SET
[ EDIT ]
|
[ DEL ]
📄 llc.h
3,179 B
SET
[ EDIT ]
|
[ DEL ]
📄 loop.h
3,512 B
SET
[ EDIT ]
|
[ DEL ]
📄 lp.h
4,205 B
SET
[ EDIT ]
|
[ DEL ]
📄 lwtunnel.h
2,194 B
SET
[ EDIT ]
|
[ DEL ]
📄 magic.h
3,531 B
SET
[ EDIT ]
|
[ DEL ]
📄 major.h
4,713 B
SET
[ EDIT ]
|
[ DEL ]
📄 map_to_7segment.h
7,251 B
SET
[ EDIT ]
|
[ DEL ]
📄 matroxfb.h
1,464 B
SET
[ EDIT ]
|
[ DEL ]
📄 max2175.h
1,035 B
SET
[ EDIT ]
|
[ DEL ]
📄 mdio.h
17,283 B
SET
[ EDIT ]
|
[ DEL ]
📄 media-bus-format.h
6,411 B
SET
[ EDIT ]
|
[ DEL ]
📄 media.h
11,942 B
SET
[ EDIT ]
|
[ DEL ]
📄 mei.h
3,475 B
SET
[ EDIT ]
|
[ DEL ]
📄 membarrier.h
7,914 B
SET
[ EDIT ]
|
[ DEL ]
📄 memfd.h
1,339 B
SET
[ EDIT ]
|
[ DEL ]
📄 mempolicy.h
2,246 B
SET
[ EDIT ]
|
[ DEL ]
📄 meye.h
2,529 B
SET
[ EDIT ]
|
[ DEL ]
📄 mic_common.h
6,499 B
SET
[ EDIT ]
|
[ DEL ]
📄 mic_ioctl.h
2,310 B
SET
[ EDIT ]
|
[ DEL ]
📄 mii.h
9,511 B
SET
[ EDIT ]
|
[ DEL ]
📄 minix_fs.h
2,122 B
SET
[ EDIT ]
|
[ DEL ]
📄 mman.h
1,400 B
SET
[ EDIT ]
|
[ DEL ]
📄 mmtimer.h
2,117 B
SET
[ EDIT ]
|
[ DEL ]
📄 module.h
270 B
SET
[ EDIT ]
|
[ DEL ]
📄 mount.h
4,561 B
SET
[ EDIT ]
|
[ DEL ]
📄 mpls.h
2,317 B
SET
[ EDIT ]
|
[ DEL ]
📄 mpls_iptunnel.h
776 B
SET
[ EDIT ]
|
[ DEL ]
📄 mptcp.h
5,623 B
SET
[ EDIT ]
|
[ DEL ]
📄 mqueue.h
2,201 B
SET
[ EDIT ]
|
[ DEL ]
📄 mroute.h
5,442 B
SET
[ EDIT ]
|
[ DEL ]
📄 mroute6.h
4,592 B
SET
[ EDIT ]
|
[ DEL ]
📄 mrp_bridge.h
1,718 B
SET
[ EDIT ]
|
[ DEL ]
📄 msdos_fs.h
6,978 B
SET
[ EDIT ]
|
[ DEL ]
📄 msg.h
3,389 B
SET
[ EDIT ]
|
[ DEL ]
📄 mtio.h
8,175 B
SET
[ EDIT ]
|
[ DEL ]
📄 n_r3964.h
2,425 B
SET
[ EDIT ]
|
[ DEL ]
📄 nbd-netlink.h
2,423 B
SET
[ EDIT ]
|
[ DEL ]
📄 nbd.h
3,039 B
SET
[ EDIT ]
|
[ DEL ]
📄 ncsi.h
3,880 B
SET
[ EDIT ]
|
[ DEL ]
📄 ndctl.h
6,693 B
SET
[ EDIT ]
|
[ DEL ]
📄 neighbour.h
5,138 B
SET
[ EDIT ]
|
[ DEL ]
📄 net.h
2,100 B
SET
[ EDIT ]
|
[ DEL ]
📄 net_dropmon.h
2,922 B
SET
[ EDIT ]
|
[ DEL ]
📄 net_namespace.h
730 B
SET
[ EDIT ]
|
[ DEL ]
📄 net_tstamp.h
5,806 B
SET
[ EDIT ]
|
[ DEL ]
📄 netconf.h
629 B
SET
[ EDIT ]
|
[ DEL ]
📄 netdevice.h
2,268 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter.h
1,888 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter_arp.h
471 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter_bridge.h
1,209 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter_decnet.h
2,050 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter_ipv4.h
2,229 B
SET
[ EDIT ]
|
[ DEL ]
📄 netfilter_ipv6.h
2,249 B
SET
[ EDIT ]
|
[ DEL ]
📄 netlink.h
11,562 B
SET
[ EDIT ]
|
[ DEL ]
📄 netlink_diag.h
1,550 B
SET
[ EDIT ]
|
[ DEL ]
📄 netrom.h
807 B
SET
[ EDIT ]
|
[ DEL ]
📄 nexthop.h
1,544 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfc.h
11,209 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs.h
4,515 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs2.h
1,468 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs3.h
2,468 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs4.h
6,614 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs4_mount.h
1,953 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs_fs.h
1,656 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs_idmap.h
2,258 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfs_mount.h
2,142 B
SET
[ EDIT ]
|
[ DEL ]
📄 nfsacl.h
733 B
SET
[ EDIT ]
|
[ DEL ]
📄 nilfs2_api.h
7,565 B
SET
[ EDIT ]
|
[ DEL ]
📄 nilfs2_ondisk.h
18,001 B
SET
[ EDIT ]
|
[ DEL ]
📄 nitro_enclaves.h
13,167 B
SET
[ EDIT ]
|
[ DEL ]
📄 nl80211.h
335,264 B
SET
[ EDIT ]
|
[ DEL ]
📄 nsfs.h
639 B
SET
[ EDIT ]
|
[ DEL ]
📄 nubus.h
8,206 B
SET
[ EDIT ]
|
[ DEL ]
📄 nvme_ioctl.h
2,127 B
SET
[ EDIT ]
|
[ DEL ]
📄 nvram.h
547 B
SET
[ EDIT ]
|
[ DEL ]
📄 omap3isp.h
21,271 B
SET
[ EDIT ]
|
[ DEL ]
📄 omapfb.h
5,940 B
SET
[ EDIT ]
|
[ DEL ]
📄 oom.h
526 B
SET
[ EDIT ]
|
[ DEL ]
📄 openat2.h
1,304 B
SET
[ EDIT ]
|
[ DEL ]
📄 openvswitch.h
41,272 B
SET
[ EDIT ]
|
[ DEL ]
📄 packet_diag.h
1,672 B
SET
[ EDIT ]
|
[ DEL ]
📄 param.h
141 B
SET
[ EDIT ]
|
[ DEL ]
📄 parport.h
3,659 B
SET
[ EDIT ]
|
[ DEL ]
📄 patchkey.h
965 B
SET
[ EDIT ]
|
[ DEL ]
📄 pci.h
1,395 B
SET
[ EDIT ]
|
[ DEL ]
📄 pci_regs.h
57,827 B
SET
[ EDIT ]
|
[ DEL ]
📄 pcitest.h
711 B
SET
[ EDIT ]
|
[ DEL ]
📄 perf_event.h
40,595 B
SET
[ EDIT ]
|
[ DEL ]
📄 personality.h
2,112 B
SET
[ EDIT ]
|
[ DEL ]
📄 pfkeyv2.h
10,569 B
SET
[ EDIT ]
|
[ DEL ]
📄 pfrut.h
7,987 B
SET
[ EDIT ]
|
[ DEL ]
📄 pg.h
2,409 B
SET
[ EDIT ]
|
[ DEL ]
📄 phantom.h
1,654 B
SET
[ EDIT ]
|
[ DEL ]
📄 phonet.h
4,640 B
SET
[ EDIT ]
|
[ DEL ]
📄 pkt_cls.h
18,511 B
SET
[ EDIT ]
|
[ DEL ]
📄 pkt_sched.h
30,296 B
SET
[ EDIT ]
|
[ DEL ]
📄 pktcdvd.h
2,702 B
SET
[ EDIT ]
|
[ DEL ]
📄 pmu.h
5,334 B
SET
[ EDIT ]
|
[ DEL ]
📄 poll.h
22 B
SET
[ EDIT ]
|
[ DEL ]
📄 posix_acl.h
1,254 B
SET
[ EDIT ]
|
[ DEL ]
📄 posix_acl_xattr.h
1,115 B
SET
[ EDIT ]
|
[ DEL ]
📄 posix_types.h
1,098 B
SET
[ EDIT ]
|
[ DEL ]
📄 ppdev.h
3,211 B
SET
[ EDIT ]
|
[ DEL ]
📄 ppp-comp.h
2,542 B
SET
[ EDIT ]
|
[ DEL ]
📄 ppp-ioctl.h
5,509 B
SET
[ EDIT ]
|
[ DEL ]
📄 ppp_defs.h
5,122 B
SET
[ EDIT ]
|
[ DEL ]
📄 pps.h
4,734 B
SET
[ EDIT ]
|
[ DEL ]
📄 pr.h
1,088 B
SET
[ EDIT ]
|
[ DEL ]
📄 prctl.h
8,023 B
SET
[ EDIT ]
|
[ DEL ]
📄 psample.h
2,271 B
SET
[ EDIT ]
|
[ DEL ]
📄 psci.h
4,343 B
SET
[ EDIT ]
|
[ DEL ]
📄 psp-sev.h
4,481 B
SET
[ EDIT ]
|
[ DEL ]
📄 ptp_clock.h
7,456 B
SET
[ EDIT ]
|
[ DEL ]
📄 ptrace.h
3,689 B
SET
[ EDIT ]
|
[ DEL ]
📄 qemu_fw_cfg.h
2,469 B
SET
[ EDIT ]
|
[ DEL ]
📄 qnx4_fs.h
2,328 B
SET
[ EDIT ]
|
[ DEL ]
📄 qnxtypes.h
624 B
SET
[ EDIT ]
|
[ DEL ]
📄 qrtr.h
878 B
SET
[ EDIT ]
|
[ DEL ]
📄 quota.h
6,306 B
SET
[ EDIT ]
|
[ DEL ]
📄 radeonfb.h
360 B
SET
[ EDIT ]
|
[ DEL ]
📄 random.h
1,385 B
SET
[ EDIT ]
|
[ DEL ]
📄 raw.h
365 B
SET
[ EDIT ]
|
[ DEL ]
📄 rds.h
9,301 B
SET
[ EDIT ]
|
[ DEL ]
📄 reboot.h
1,358 B
SET
[ EDIT ]
|
[ DEL ]
📄 reiserfs_fs.h
775 B
SET
[ EDIT ]
|
[ DEL ]
📄 reiserfs_xattr.h
533 B
SET
[ EDIT ]
|
[ DEL ]
📄 resource.h
2,362 B
SET
[ EDIT ]
|
[ DEL ]
📄 rfkill.h
6,623 B
SET
[ EDIT ]
|
[ DEL ]
📄 rio_cm_cdev.h
3,248 B
SET
[ EDIT ]
|
[ DEL ]
📄 rio_mport_cdev.h
9,330 B
SET
[ EDIT ]
|
[ DEL ]
📄 romfs_fs.h
1,238 B
SET
[ EDIT ]
|
[ DEL ]
📄 rose.h
2,232 B
SET
[ EDIT ]
|
[ DEL ]
📄 route.h
2,392 B
SET
[ EDIT ]
|
[ DEL ]
📄 rpmsg.h
554 B
SET
[ EDIT ]
|
[ DEL ]
📄 rseq.h
4,919 B
SET
[ EDIT ]
|
[ DEL ]
📄 rtc.h
4,024 B
SET
[ EDIT ]
|
[ DEL ]
📄 rtnetlink.h
20,242 B
SET
[ EDIT ]
|
[ DEL ]
📄 rxrpc.h
5,095 B
SET
[ EDIT ]
|
[ DEL ]
📄 scc.h
4,612 B
SET
[ EDIT ]
|
[ DEL ]
📄 sched.h
2,812 B
SET
[ EDIT ]
|
[ DEL ]
📄 scif_ioctl.h
6,382 B
SET
[ EDIT ]
|
[ DEL ]
📄 screen_info.h
2,494 B
SET
[ EDIT ]
|
[ DEL ]
📄 sctp.h
36,099 B
SET
[ EDIT ]
|
[ DEL ]
📄 sdla.h
2,861 B
SET
[ EDIT ]
|
[ DEL ]
📄 seccomp.h
2,299 B
SET
[ EDIT ]
|
[ DEL ]
📄 securebits.h
2,719 B
SET
[ EDIT ]
|
[ DEL ]
📄 sed-opal.h
3,290 B
SET
[ EDIT ]
|
[ DEL ]
📄 seg6.h
1,180 B
SET
[ EDIT ]
|
[ DEL ]
📄 seg6_genl.h
599 B
SET
[ EDIT ]
|
[ DEL ]
📄 seg6_hmac.h
433 B
SET
[ EDIT ]
|
[ DEL ]
📄 seg6_iptunnel.h
1,293 B
SET
[ EDIT ]
|
[ DEL ]
📄 seg6_local.h
2,070 B
SET
[ EDIT ]
|
[ DEL ]
📄 selinux_netlink.h
1,221 B
SET
[ EDIT ]
|
[ DEL ]
📄 sem.h
3,086 B
SET
[ EDIT ]
|
[ DEL ]
📄 serial.h
3,881 B
SET
[ EDIT ]
|
[ DEL ]
📄 serial_core.h
6,260 B
SET
[ EDIT ]
|
[ DEL ]
📄 serial_reg.h
15,496 B
SET
[ EDIT ]
|
[ DEL ]
📄 serio.h
2,052 B
SET
[ EDIT ]
|
[ DEL ]
📄 sev-guest.h
2,303 B
SET
[ EDIT ]
|
[ DEL ]
📄 shm.h
3,826 B
SET
[ EDIT ]
|
[ DEL ]
📄 signal.h
403 B
SET
[ EDIT ]
|
[ DEL ]
📄 signalfd.h
1,248 B
SET
[ EDIT ]
|
[ DEL ]
📄 smc.h
8,528 B
SET
[ EDIT ]
|
[ DEL ]
📄 smc_diag.h
2,743 B
SET
[ EDIT ]
|
[ DEL ]
📄 smiapp.h
1,058 B
SET
[ EDIT ]
|
[ DEL ]
📄 snmp.h
13,663 B
SET
[ EDIT ]
|
[ DEL ]
📄 sock_diag.h
1,316 B
SET
[ EDIT ]
|
[ DEL ]
📄 socket.h
916 B
SET
[ EDIT ]
|
[ DEL ]
📄 sockios.h
6,106 B
SET
[ EDIT ]
|
[ DEL ]
📄 sonet.h
2,305 B
SET
[ EDIT ]
|
[ DEL ]
📄 sonypi.h
5,324 B
SET
[ EDIT ]
|
[ DEL ]
📄 sound.h
1,252 B
SET
[ EDIT ]
|
[ DEL ]
📄 soundcard.h
46,170 B
SET
[ EDIT ]
|
[ DEL ]
📄 stat.h
6,367 B
SET
[ EDIT ]
|
[ DEL ]
📄 stddef.h
1,571 B
SET
[ EDIT ]
|
[ DEL ]
📄 stm.h
1,290 B
SET
[ EDIT ]
|
[ DEL ]
📄 string.h
296 B
SET
[ EDIT ]
|
[ DEL ]
📄 suspend_ioctls.h
1,431 B
SET
[ EDIT ]
|
[ DEL ]
📄 swab.h
7,018 B
SET
[ EDIT ]
|
[ DEL ]
📄 switchtec_ioctl.h
5,272 B
SET
[ EDIT ]
|
[ DEL ]
📄 sync_file.h
2,898 B
SET
[ EDIT ]
|
[ DEL ]
📄 synclink.h
9,000 B
SET
[ EDIT ]
|
[ DEL ]
📄 sysctl.h
25,912 B
SET
[ EDIT ]
|
[ DEL ]
📄 sysinfo.h
1,049 B
SET
[ EDIT ]
|
[ DEL ]
📄 target_core_user.h
4,557 B
SET
[ EDIT ]
|
[ DEL ]
📄 taskstats.h
7,180 B
SET
[ EDIT ]
|
[ DEL ]
📄 tcp.h
9,935 B
SET
[ EDIT ]
|
[ DEL ]
📄 tcp_metrics.h
1,549 B
SET
[ EDIT ]
|
[ DEL ]
📄 tdx-guest.h
1,320 B
SET
[ EDIT ]
|
[ DEL ]
📄 tee.h
13,172 B
SET
[ EDIT ]
|
[ DEL ]
📄 termios.h
506 B
SET
[ EDIT ]
|
[ DEL ]
📄 thermal.h
3,324 B
SET
[ EDIT ]
|
[ DEL ]
📄 time.h
1,763 B
SET
[ EDIT ]
|
[ DEL ]
📄 time_types.h
1,190 B
SET
[ EDIT ]
|
[ DEL ]
📄 timerfd.h
951 B
SET
[ EDIT ]
|
[ DEL ]
📄 times.h
278 B
SET
[ EDIT ]
|
[ DEL ]
📄 timex.h
6,444 B
SET
[ EDIT ]
|
[ DEL ]
📄 tiocl.h
1,729 B
SET
[ EDIT ]
|
[ DEL ]
📄 tipc.h
8,805 B
SET
[ EDIT ]
|
[ DEL ]
📄 tipc_config.h
14,682 B
SET
[ EDIT ]
|
[ DEL ]
📄 tipc_netlink.h
9,395 B
SET
[ EDIT ]
|
[ DEL ]
📄 tipc_sockets_diag.h
483 B
SET
[ EDIT ]
|
[ DEL ]
📄 tls.h
4,303 B
SET
[ EDIT ]
|
[ DEL ]
📄 toshiba.h
1,945 B
SET
[ EDIT ]
|
[ DEL ]
📄 tty.h
1,600 B
SET
[ EDIT ]
|
[ DEL ]
📄 tty_flags.h
4,527 B
SET
[ EDIT ]
|
[ DEL ]
📄 types.h
1,681 B
SET
[ EDIT ]
|
[ DEL ]
📄 udf_fs_i.h
697 B
SET
[ EDIT ]
|
[ DEL ]
📄 udp.h
1,676 B
SET
[ EDIT ]
|
[ DEL ]
📄 uhid.h
4,655 B
SET
[ EDIT ]
|
[ DEL ]
📄 uinput.h
9,276 B
SET
[ EDIT ]
|
[ DEL ]
📄 uio.h
781 B
SET
[ EDIT ]
|
[ DEL ]
📄 uleds.h
813 B
SET
[ EDIT ]
|
[ DEL ]
📄 ultrasound.h
4,562 B
SET
[ EDIT ]
|
[ DEL ]
📄 un.h
384 B
SET
[ EDIT ]
|
[ DEL ]
📄 unistd.h
220 B
SET
[ EDIT ]
|
[ DEL ]
📄 unix_diag.h
1,253 B
SET
[ EDIT ]
|
[ DEL ]
📄 usbdevice_fs.h
8,374 B
SET
[ EDIT ]
|
[ DEL ]
📄 usbip.h
655 B
SET
[ EDIT ]
|
[ DEL ]
📄 userfaultfd.h
7,759 B
SET
[ EDIT ]
|
[ DEL ]
📄 userio.h
1,516 B
SET
[ EDIT ]
|
[ DEL ]
📄 utime.h
215 B
SET
[ EDIT ]
|
[ DEL ]
📄 utsname.h
684 B
SET
[ EDIT ]
|
[ DEL ]
📄 uuid.h
1,371 B
SET
[ EDIT ]
|
[ DEL ]
📄 uvcvideo.h
2,634 B
SET
[ EDIT ]
|
[ DEL ]
📄 v4l2-common.h
4,177 B
SET
[ EDIT ]
|
[ DEL ]
📄 v4l2-controls.h
51,777 B
SET
[ EDIT ]
|
[ DEL ]
📄 v4l2-dv-timings.h
31,562 B
SET
[ EDIT ]
|
[ DEL ]
📄 v4l2-mediabus.h
5,144 B
SET
[ EDIT ]
|
[ DEL ]
📄 v4l2-subdev.h
6,096 B
SET
[ EDIT ]
|
[ DEL ]
📄 vbox_err.h
7,257 B
SET
[ EDIT ]
|
[ DEL ]
📄 vbox_vmmdev_types.h
8,296 B
SET
[ EDIT ]
|
[ DEL ]
📄 vboxguest.h
8,729 B
SET
[ EDIT ]
|
[ DEL ]
📄 vdpa.h
1,431 B
SET
[ EDIT ]
|
[ DEL ]
📄 veth.h
224 B
SET
[ EDIT ]
|
[ DEL ]
📄 vfio.h
52,245 B
SET
[ EDIT ]
|
[ DEL ]
📄 vfio_ccw.h
1,257 B
SET
[ EDIT ]
|
[ DEL ]
📄 vfio_zdev.h
2,542 B
SET
[ EDIT ]
|
[ DEL ]
📄 vhost.h
6,418 B
SET
[ EDIT ]
|
[ DEL ]
📄 vhost_types.h
4,024 B
SET
[ EDIT ]
|
[ DEL ]
📄 videodev2.h
90,983 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_9p.h
2,041 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_balloon.h
5,274 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_blk.h
6,823 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_bt.h
787 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_config.h
4,063 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_console.h
3,151 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_crypto.h
13,874 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_fs.h
587 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_gpu.h
11,454 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_ids.h
3,269 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_input.h
2,506 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_iommu.h
3,793 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_mem.h
7,157 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_mmio.h
4,969 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_net.h
10,564 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_pci.h
7,406 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_ring.h
7,526 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_rng.h
265 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_scsi.h
6,035 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_snd.h
9,304 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_types.h
2,168 B
SET
[ EDIT ]
|
[ DEL ]
📄 virtio_vsock.h
3,101 B
SET
[ EDIT ]
|
[ DEL ]
📄 vm_sockets.h
6,509 B
SET
[ EDIT ]
|
[ DEL ]
📄 vm_sockets_diag.h
978 B
SET
[ EDIT ]
|
[ DEL ]
📄 vmcore.h
446 B
SET
[ EDIT ]
|
[ DEL ]
📄 vsockmon.h
1,895 B
SET
[ EDIT ]
|
[ DEL ]
📄 vt.h
3,074 B
SET
[ EDIT ]
|
[ DEL ]
📄 vtpm_proxy.h
1,734 B
SET
[ EDIT ]
|
[ DEL ]
📄 wait.h
697 B
SET
[ EDIT ]
|
[ DEL ]
📄 wanrouter.h
468 B
SET
[ EDIT ]
|
[ DEL ]
📄 watchdog.h
2,350 B
SET
[ EDIT ]
|
[ DEL ]
📄 wimax.h
8,371 B
SET
[ EDIT ]
|
[ DEL ]
📄 wireless.h
42,725 B
SET
[ EDIT ]
|
[ DEL ]
📄 wmi.h
1,843 B
SET
[ EDIT ]
|
[ DEL ]
📄 x25.h
3,562 B
SET
[ EDIT ]
|
[ DEL ]
📄 xattr.h
2,875 B
SET
[ EDIT ]
|
[ DEL ]
📄 xdp_diag.h
1,468 B
SET
[ EDIT ]
|
[ DEL ]
📄 xfrm.h
12,020 B
SET
[ EDIT ]
|
[ DEL ]
📄 xilinx-v4l2-controls.h
2,976 B
SET
[ EDIT ]
|
[ DEL ]
📄 zorro.h
3,266 B
SET
[ EDIT ]
|
[ DEL ]
📄 zorro_ids.h
29,963 B
SET
[ EDIT ]
|
[ DEL ]
DELETE SELECTED
[ CLOSE ]
EDIT: pci_regs.h
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * PCI standard defines * Copyright 1994, Drew Eckhardt * Copyright 1997--1999 Martin Mares <mj@ucw.cz> * * For more information, please consult the following manuals (look at * http://www.pcisig.com/ for how to get them): * * PCI BIOS Specification * PCI Local Bus Specification * PCI to PCI Bridge Specification * PCI System Design Guide * * For HyperTransport information, please consult the following manuals * from http://www.hypertransport.org : * * The HyperTransport I/O Link Specification */ #ifndef LINUX_PCI_REGS_H #define LINUX_PCI_REGS_H /* * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of * configuration space. */ #define PCI_CFG_SPACE_SIZE 256 #define PCI_CFG_SPACE_EXP_SIZE 4096 /* * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */ #define PCI_STD_HEADER_SIZEOF 64 #define PCI_STD_NUM_BARS 6 #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ #define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ #define PCI_REVISION_ID 0x08 /* Revision ID */ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ #define PCI_HEADER_TYPE 0x0e /* 8 bits */ #define PCI_HEADER_TYPE_MASK 0x7f #define PCI_HEADER_TYPE_NORMAL 0 #define PCI_HEADER_TYPE_BRIDGE 1 #define PCI_HEADER_TYPE_CARDBUS 2 #define PCI_BIST 0x0f /* 8 bits */ #define PCI_BIST_CODE_MASK 0x0f /* Return result */ #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ /* * Base addresses specify locations in memory or I/O space. * Decoded size can be determined by writing a value of * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ #define PCI_BASE_ADDRESS_SPACE_IO 0x01 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) /* bit 1 is reserved if address_space = 1 */ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c #define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffU) #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ /* 0x35-0x3b are reserved */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ #define PCI_MIN_GNT 0x3e /* 8 bits */ #define PCI_MAX_LAT 0x3f /* 8 bits */ /* Header type 1 (PCI-to-PCI bridges) */ #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ #define PCI_IO_LIMIT 0x1d #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ #define PCI_IO_RANGE_TYPE_16 0x00 #define PCI_IO_RANGE_TYPE_32 0x01 #define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ #define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ #define PCI_MEMORY_LIMIT 0x22 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL #define PCI_MEMORY_RANGE_MASK (~0x0fUL) #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ #define PCI_PREF_MEMORY_LIMIT 0x26 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL #define PCI_PREF_RANGE_TYPE_32 0x00 #define PCI_PREF_RANGE_TYPE_64 0x01 #define PCI_PREF_RANGE_MASK (~0x0fUL) #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ #define PCI_PREF_LIMIT_UPPER32 0x2c #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ #define PCI_IO_LIMIT_UPPER16 0x32 /* 0x34 same as for htype 0 */ /* 0x35-0x3b is reserved */ #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ /* 0x3c-0x3d are same as for htype 0 */ #define PCI_BRIDGE_CONTROL 0x3e #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ /* Header type 2 (CardBus bridges) */ #define PCI_CB_CAPABILITY_LIST 0x14 /* 0x15 reserved */ #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ #define PCI_CB_MEMORY_BASE_0 0x1c #define PCI_CB_MEMORY_LIMIT_0 0x20 #define PCI_CB_MEMORY_BASE_1 0x24 #define PCI_CB_MEMORY_LIMIT_1 0x28 #define PCI_CB_IO_BASE_0 0x2c #define PCI_CB_IO_BASE_0_HI 0x2e #define PCI_CB_IO_LIMIT_0 0x30 #define PCI_CB_IO_LIMIT_0_HI 0x32 #define PCI_CB_IO_BASE_1 0x34 #define PCI_CB_IO_BASE_1_HI 0x36 #define PCI_CB_IO_LIMIT_1 0x38 #define PCI_CB_IO_LIMIT_1_HI 0x3a #define PCI_CB_IO_RANGE_MASK (~0x03UL) /* 0x3c-0x3d are same as for htype 0 */ #define PCI_CB_BRIDGE_CONTROL 0x3e #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ #define PCI_CB_BRIDGE_CTL_SERR 0x02 #define PCI_CB_BRIDGE_CTL_ISA 0x04 #define PCI_CB_BRIDGE_CTL_VGA 0x08 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 #define PCI_CB_SUBSYSTEM_ID 0x42 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ /* 0x48-0x7f reserved */ /* Capability lists */ #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ #define PCI_CAP_ID_DBG 0x0A /* Debug port */ #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ #define PCI_CAP_ID_MAX PCI_CAP_ID_EA #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 /* Power Management Registers */ #define PCI_PM_PMC 2 /* PM Capabilities Register */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ #define PCI_PM_DATA_REGISTER 7 /* (??) */ #define PCI_PM_SIZEOF 8 /* AGP registers */ #define PCI_AGP_VERSION 2 /* BCD version number */ #define PCI_AGP_RFU 3 /* Rest of capability flags */ #define PCI_AGP_STATUS 4 /* Status register */ #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ #define PCI_AGP_COMMAND 8 /* Control register */ #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ #define PCI_AGP_SIZEOF 12 /* Vital Product Data */ #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ #define PCI_CAP_VPD_SIZEOF 8 /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ /* Message Signalled Interrupt registers */ #define PCI_MSI_FLAGS 2 /* Message Control */ #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ #define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ #define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ #define PCI_MSI_RFU 3 /* Rest of capability flags */ #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ /* MSI-X registers (in MSI-X capability) */ #define PCI_MSIX_FLAGS 2 /* Message Control */ #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ #define PCI_MSIX_TABLE 4 /* Table offset */ #define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ #define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ #define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ /* MSI-X Table entry format (in memory mapped by a BAR) */ #define PCI_MSIX_ENTRY_SIZE 16 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */ #define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */ #define PCI_MSIX_ENTRY_DATA 8 /* Message Data */ #define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */ #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ #define PCI_CHSWP_PI 0x30 /* Programming Interface */ #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ /* PCI Advanced Feature registers */ #define PCI_AF_LENGTH 2 #define PCI_AF_CAP 3 #define PCI_AF_CAP_TP 0x01 #define PCI_AF_CAP_FLR 0x02 #define PCI_AF_CTRL 4 #define PCI_AF_CTRL_FLR 0x01 #define PCI_AF_STATUS 5 #define PCI_AF_STATUS_TP 0x01 #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ /* PCI Enhanced Allocation registers */ #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ #define PCI_EA_ES 0x00000007 /* Entry Size */ #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ /* EA fixed Secondary and Subordinate bus numbers for Bridge */ #define PCI_EA_SEC_BUS_MASK 0xff #define PCI_EA_SUB_BUS_MASK 0xff00 #define PCI_EA_SUB_BUS_SHIFT 8 /* 0-5 map to BARs 0-5 respectively */ #define PCI_EA_BEI_BAR0 0 #define PCI_EA_BEI_BAR5 5 #define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */ #define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */ #define PCI_EA_BEI_ROM 8 /* Expansion ROM */ /* 9-14 map to VF BARs 0-5 respectively */ #define PCI_EA_BEI_VF_BAR0 9 #define PCI_EA_BEI_VF_BAR5 14 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */ #define PCI_EA_PP 0x0000ff00 /* Primary Properties */ #define PCI_EA_SP 0x00ff0000 /* Secondary Properties */ #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */ #define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ #define PCI_EA_P_IO 0x02 /* I/O Space */ #define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ #define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ #define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ /* 0x08-0xfc reserved */ #define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ #define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ #define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ #define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */ #define PCI_EA_BASE 4 /* Base Address Offset */ #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ /* bit 0 is reserved */ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI-X registers (Type 0 (non-bridge) devices) */ #define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ /* Max # of outstanding split transactions */ #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ #define PCI_X_ECC_CSR 8 /* ECC control and status */ #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ /* PCI-X registers (Type 1 (bridge) devices) */ #define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ #define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ /* PCI Bridge Subsystem ID registers */ #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ /* PCI Express capability registers */ #define PCI_EXP_FLAGS 2 /* Capabilities register */ #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ #define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ #define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ #define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ #define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_DEVSTA 10 /* Device Status */ #define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ #define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ #define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ #define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ #define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */ #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ #define PCI_EXP_RTCTL 28 /* Root Control */ #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_RTSTA 32 /* Root Status */ #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ /* * The Device Capabilities 2, Device Status 2, Device Control 2, * Link Capabilities 2, Link Status 2, Link Control 2, * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers * are only present on devices with PCIe Capability version 2. * Use pcie_capability_read_word() and similar interfaces to use them * safely. */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */ #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKCTL2_TLS 0x000f #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DVSEC #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ #define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ #define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ /* Same bits as above */ #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ /* Same bits as above */ #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ /* Same bits as above */ #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ #define PCI_ERR_ROOT_STATUS 48 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ /* Virtual Channel */ #define PCI_VC_PORT_CAP1 4 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 #define PCI_VC_PORT_CAP2 8 #define PCI_VC_CAP2_32_PHASE 0x00000002 #define PCI_VC_CAP2_64_PHASE 0x00000004 #define PCI_VC_CAP2_128_PHASE 0x00000008 #define PCI_VC_CAP2_ARB_OFF 0xff000000 #define PCI_VC_PORT_CTRL 12 #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 #define PCI_VC_PORT_STATUS 14 #define PCI_VC_PORT_STATUS_TABLE 0x00000001 #define PCI_VC_RES_CAP 16 #define PCI_VC_RES_CAP_32_PHASE 0x00000002 #define PCI_VC_RES_CAP_64_PHASE 0x00000004 #define PCI_VC_RES_CAP_128_PHASE 0x00000008 #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 #define PCI_VC_RES_CAP_256_PHASE 0x00000020 #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 #define PCI_VC_RES_CTRL 20 #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 #define PCI_VC_RES_CTRL_ID 0x07000000 #define PCI_VC_RES_CTRL_ENABLE 0x80000000 #define PCI_VC_RES_STATUS 26 #define PCI_VC_RES_STATUS_TABLE 0x00000001 #define PCI_VC_RES_STATUS_NEGO 0x00000002 #define PCI_CAP_VC_BASE_SIZEOF 0x10 #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C /* Power Budgeting */ #define PCI_PWR_DSR 4 /* Data Select Register */ #define PCI_PWR_DATA 8 /* Data Register */ #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ #define PCI_EXT_CAP_PWR_SIZEOF 16 /* Root Complex Event Collector Endpoint Association */ #define PCI_RCEC_RCIEP_BITMAP 4 /* Associated Bitmap for RCiEPs */ #define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */ #define PCI_RCEC_BUSN_REG_VER 0x02 /* Least version with BUSN present */ #define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff) #define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff) /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) /* * HyperTransport sub capability types * * Unfortunately there are both 3 bit and 5 bit capability types defined * in the HT spec, catering for that is a little messy. You probably don't * want to use these directly, just use pci_find_ht_capability() and it * will do the right thing for you. */ #define HT_3BIT_CAP_MASK 0xE0 #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ #define HT_5BIT_CAP_MASK 0xF8 #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ #define HT_MSI_FLAGS 0x02 /* Offset to flags */ #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ /* Alternative Routing-ID Interpretation */ #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ #define PCI_EXT_CAP_ARI_SIZEOF 8 /* Address Translation Service */ #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */ #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ #define PCI_EXT_CAP_ATS_SIZEOF 8 /* Page Request Interface */ #define PCI_PRI_CTRL 0x04 /* PRI control register */ #define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ #define PCI_PRI_CTRL_RESET 0x0002 /* Reset */ #define PCI_PRI_STATUS 0x06 /* PRI status register */ #define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ #define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ #define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ #define PCI_EXT_CAP_PRI_SIZEOF 16 /* Process Address Space ID */ #define PCI_PASID_CAP 0x04 /* PASID feature register */ #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ #define PCI_PASID_CTRL 0x06 /* PASID control register */ #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ #define PCI_EXT_CAP_PASID_SIZEOF 8 /* Single Root I/O Virtualization */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */ #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ #define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */ #define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */ #define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */ #define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */ #define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ #define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */ #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ #define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ #define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ #define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ #define PCI_EXT_CAP_SRIOV_SIZEOF 64 #define PCI_LTR_MAX_SNOOP_LAT 0x4 #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 #define PCI_LTR_VALUE_MASK 0x000003ff #define PCI_LTR_SCALE_MASK 0x00001c00 #define PCI_LTR_SCALE_SHIFT 10 #define PCI_EXT_CAP_LTR_SIZEOF 8 /* Access Control Service */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_SV 0x0001 /* Source Validation */ #define PCI_ACS_TB 0x0002 /* Translation Blocking */ #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ #define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ /* SATA capability */ #define PCI_SATA_REGS 4 /* SATA REGs specifier */ #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ #define PCI_SATA_SIZEOF_SHORT 8 #define PCI_SATA_SIZEOF_LONG 16 /* Resizable BARs */ #define PCI_REBAR_CAP 4 /* capability register */ #define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ #define PCI_REBAR_CTRL 8 /* control register */ #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ #define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */ /* Dynamic Power Allocation */ #define PCI_DPA_CAP 4 /* capability register */ #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ /* TPH Requester */ #define PCI_TPH_CAP 4 /* capability register */ #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ #define PCI_TPH_LOC_NONE 0x000 /* no location */ #define PCI_TPH_LOC_CAP 0x200 /* in capability */ #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ #define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ #define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ /* Downstream Port Containment */ #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */ #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */ #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */ #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */ #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ #define PCI_EXP_DPC_CTL 6 /* DPC control */ #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */ #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ #define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */ #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */ #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */ /* Precision Time Measurement */ #define PCI_PTM_CAP 0x04 /* PTM Capability */ #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ #define PCI_PTM_CTRL 0x08 /* PTM Control */ #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ /* ASPM L1 PM Substates */ #define PCI_L1SS_CAP 0x04 /* Capabilities Register */ #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ #define PCI_L1SS_CTL1_L1_2_MASK 0x00000005 #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f #define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ #define PCI_DVSEC_HEADER1_VID(x) ((x) & 0xffff) #define PCI_DVSEC_HEADER1_REV(x) (((x) >> 16) & 0xf) #define PCI_DVSEC_HEADER1_LEN(x) (((x) >> 20) & 0xfff) #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ #define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff) #endif /* LINUX_PCI_REGS_H */