Geforce File Manager

NAME	SIZE	ACTIONS
📁 sanitizer		[ DEL ]
📄 adxintrin.h	2,865 B	[ EDIT ] \| [ DEL ]
📄 ammintrin.h	3,216 B	[ EDIT ] \| [ DEL ]
📄 avx2intrin.h	58,632 B	[ EDIT ] \| [ DEL ]
📄 avx5124fmapsintrin.h	6,535 B	[ EDIT ] \| [ DEL ]
📄 avx5124vnniwintrin.h	4,256 B	[ EDIT ] \| [ DEL ]
📄 avx512bitalgintrin.h	8,850 B	[ EDIT ] \| [ DEL ]
📄 avx512bwintrin.h	101,510 B	[ EDIT ] \| [ DEL ]
📄 avx512cdintrin.h	5,822 B	[ EDIT ] \| [ DEL ]
📄 avx512dqintrin.h	85,372 B	[ EDIT ] \| [ DEL ]
📄 avx512erintrin.h	12,965 B	[ EDIT ] \| [ DEL ]
📄 avx512fintrin.h	486,788 B	[ EDIT ] \| [ DEL ]
📄 avx512ifmaintrin.h	3,430 B	[ EDIT ] \| [ DEL ]
📄 avx512ifmavlintrin.h	5,385 B	[ EDIT ] \| [ DEL ]
📄 avx512pfintrin.h	10,289 B	[ EDIT ] \| [ DEL ]
📄 avx512vbmi2intrin.h	19,810 B	[ EDIT ] \| [ DEL ]
📄 avx512vbmi2vlintrin.h	37,120 B	[ EDIT ] \| [ DEL ]
📄 avx512vbmiintrin.h	4,921 B	[ EDIT ] \| [ DEL ]
📄 avx512vbmivlintrin.h	8,364 B	[ EDIT ] \| [ DEL ]
📄 avx512vlbwintrin.h	143,851 B	[ EDIT ] \| [ DEL ]
📄 avx512vldqintrin.h	61,317 B	[ EDIT ] \| [ DEL ]
📄 avx512vlintrin.h	423,976 B	[ EDIT ] \| [ DEL ]
📄 avx512vnniintrin.h	4,969 B	[ EDIT ] \| [ DEL ]
📄 avx512vnnivlintrin.h	8,244 B	[ EDIT ] \| [ DEL ]
📄 avx512vpopcntdqintrin.h	3,110 B	[ EDIT ] \| [ DEL ]
📄 avx512vpopcntdqvlintrin.h	4,667 B	[ EDIT ] \| [ DEL ]
📄 avxintrin.h	50,613 B	[ EDIT ] \| [ DEL ]
📄 bmi2intrin.h	3,388 B	[ EDIT ] \| [ DEL ]
📄 bmiintrin.h	5,628 B	[ EDIT ] \| [ DEL ]
📄 bmmintrin.h	1,154 B	[ EDIT ] \| [ DEL ]
📄 cet.h	2,665 B	[ EDIT ] \| [ DEL ]
📄 cetintrin.h	3,333 B	[ EDIT ] \| [ DEL ]
📄 clflushoptintrin.h	1,663 B	[ EDIT ] \| [ DEL ]
📄 clwbintrin.h	1,585 B	[ EDIT ] \| [ DEL ]
📄 clzerointrin.h	1,491 B	[ EDIT ] \| [ DEL ]
📄 cpuid.h	8,926 B	[ EDIT ] \| [ DEL ]
📄 cross-stdarg.h	2,558 B	[ EDIT ] \| [ DEL ]
📄 emmintrin.h	51,033 B	[ EDIT ] \| [ DEL ]
📄 f16cintrin.h	3,410 B	[ EDIT ] \| [ DEL ]
📄 float.h	16,917 B	[ EDIT ] \| [ DEL ]
📄 fma4intrin.h	9,132 B	[ EDIT ] \| [ DEL ]
📄 fmaintrin.h	10,536 B	[ EDIT ] \| [ DEL ]
📄 fxsrintrin.h	2,108 B	[ EDIT ] \| [ DEL ]
📄 gcov.h	1,394 B	[ EDIT ] \| [ DEL ]
📄 gfniintrin.h	15,050 B	[ EDIT ] \| [ DEL ]
📄 ia32intrin.h	7,873 B	[ EDIT ] \| [ DEL ]
📄 immintrin.h	5,453 B	[ EDIT ] \| [ DEL ]
📄 iso646.h	1,272 B	[ EDIT ] \| [ DEL ]
📄 limits.h	6,089 B	[ EDIT ] \| [ DEL ]
📄 lwpintrin.h	3,400 B	[ EDIT ] \| [ DEL ]
📄 lzcntintrin.h	2,398 B	[ EDIT ] \| [ DEL ]
📄 mm3dnow.h	7,076 B	[ EDIT ] \| [ DEL ]
📄 mm_malloc.h	1,783 B	[ EDIT ] \| [ DEL ]
📄 mmintrin.h	31,354 B	[ EDIT ] \| [ DEL ]
📄 movdirintrin.h	2,342 B	[ EDIT ] \| [ DEL ]
📄 mwaitxintrin.h	1,747 B	[ EDIT ] \| [ DEL ]
📄 nmmintrin.h	1,288 B	[ EDIT ] \| [ DEL ]
📄 omp.h	5,995 B	[ EDIT ] \| [ DEL ]
📄 openacc.h	4,639 B	[ EDIT ] \| [ DEL ]
📄 pconfigintrin.h	2,348 B	[ EDIT ] \| [ DEL ]
📄 pkuintrin.h	1,741 B	[ EDIT ] \| [ DEL ]
📄 pmmintrin.h	4,368 B	[ EDIT ] \| [ DEL ]
📄 popcntintrin.h	1,750 B	[ EDIT ] \| [ DEL ]
📄 prfchwintrin.h	1,447 B	[ EDIT ] \| [ DEL ]
📄 rdseedintrin.h	2,017 B	[ EDIT ] \| [ DEL ]
📄 rtmintrin.h	2,733 B	[ EDIT ] \| [ DEL ]
📄 sgxintrin.h	7,091 B	[ EDIT ] \| [ DEL ]
📄 shaintrin.h	3,204 B	[ EDIT ] \| [ DEL ]
📄 smmintrin.h	28,405 B	[ EDIT ] \| [ DEL ]
📄 stdalign.h	1,210 B	[ EDIT ] \| [ DEL ]
📄 stdarg.h	4,072 B	[ EDIT ] \| [ DEL ]
📄 stdatomic.h	9,321 B	[ EDIT ] \| [ DEL ]
📄 stdbool.h	1,524 B	[ EDIT ] \| [ DEL ]
📄 stddef.h	14,140 B	[ EDIT ] \| [ DEL ]
📄 stdfix.h	6,000 B	[ EDIT ] \| [ DEL ]
📄 stdint-gcc.h	9,457 B	[ EDIT ] \| [ DEL ]
📄 stdint.h	328 B	[ EDIT ] \| [ DEL ]
📄 stdnoreturn.h	1,136 B	[ EDIT ] \| [ DEL ]
📄 syslimits.h	330 B	[ EDIT ] \| [ DEL ]
📄 tbmintrin.h	5,242 B	[ EDIT ] \| [ DEL ]
📄 tmmintrin.h	8,343 B	[ EDIT ] \| [ DEL ]
📄 unwind.h	10,905 B	[ EDIT ] \| [ DEL ]
📄 vaesintrin.h	4,655 B	[ EDIT ] \| [ DEL ]
📄 varargs.h	139 B	[ EDIT ] \| [ DEL ]
📄 vpclmulqdqintrin.h	3,478 B	[ EDIT ] \| [ DEL ]
📄 wbnoinvdintrin.h	1,620 B	[ EDIT ] \| [ DEL ]
📄 wmmintrin.h	4,656 B	[ EDIT ] \| [ DEL ]
📄 x86intrin.h	2,111 B	[ EDIT ] \| [ DEL ]
📄 xmmintrin.h	42,210 B	[ EDIT ] \| [ DEL ]
📄 xopintrin.h	28,568 B	[ EDIT ] \| [ DEL ]
📄 xsavecintrin.h	1,821 B	[ EDIT ] \| [ DEL ]
📄 xsaveintrin.h	2,524 B	[ EDIT ] \| [ DEL ]
📄 xsaveoptintrin.h	1,903 B	[ EDIT ] \| [ DEL ]
📄 xsavesintrin.h	2,157 B	[ EDIT ] \| [ DEL ]
📄 xtestintrin.h	1,687 B	[ EDIT ] \| [ DEL ]

[ CLOSE ]

EDIT: ia32intrin.h

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

GCC is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

Under Section 7 of GPL version 3, you are granted additional
   permissions described in the GCC Runtime Library Exception, version
   3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and
   a copy of the GCC Runtime Library Exception along with this program;
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
   <http://www.gnu.org/licenses/>.  */

#ifndef _X86INTRIN_H_INCLUDED
# error "Never use <ia32intrin.h> directly; include <x86intrin.h> instead."
#endif

/* 32bit bsf */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bsfd (int __X)
{
  return __builtin_ctz (__X);
}

/* 32bit bsr */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bsrd (int __X)
{
  return __builtin_ia32_bsrsi (__X);
}

/* 32bit bswap */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bswapd (int __X)
{
  return __builtin_bswap32 (__X);
}

#ifndef __iamcu__

#ifndef __SSE4_2__
#pragma GCC push_options
#pragma GCC target("sse4.2")
#define __DISABLE_SSE4_2__
#endif /* __SSE4_2__ */

/* 32bit accumulate CRC32 (polynomial 0x11EDC6F41) value.  */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__crc32b (unsigned int __C, unsigned char __V)
{
  return __builtin_ia32_crc32qi (__C, __V);
}

extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__crc32w (unsigned int __C, unsigned short __V)
{
  return __builtin_ia32_crc32hi (__C, __V);
}

extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__crc32d (unsigned int __C, unsigned int __V)
{
  return __builtin_ia32_crc32si (__C, __V);
}

#ifdef __DISABLE_SSE4_2__
#undef __DISABLE_SSE4_2__
#pragma GCC pop_options
#endif /* __DISABLE_SSE4_2__ */

#endif /* __iamcu__ */

/* 32bit popcnt */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__popcntd (unsigned int __X)
{
  return __builtin_popcount (__X);
}

#ifndef __iamcu__

/* rdpmc */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rdpmc (int __S)
{
  return __builtin_ia32_rdpmc (__S);
}

#endif /* __iamcu__ */

/* rdtsc */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rdtsc (void)
{
  return __builtin_ia32_rdtsc ();
}

#ifndef __iamcu__

/* rdtscp */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rdtscp (unsigned int *__A)
{
  return __builtin_ia32_rdtscp (__A);
}

#endif /* __iamcu__ */

/* 8bit rol */
extern __inline unsigned char
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rolb (unsigned char __X, int __C)
{
  return __builtin_ia32_rolqi (__X, __C);
}

/* 16bit rol */
extern __inline unsigned short
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rolw (unsigned short __X, int __C)
{
  return __builtin_ia32_rolhi (__X, __C);
}

/* 32bit rol */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rold (unsigned int __X, int __C)
{
  __C &= 31;
  return (__X << __C) | (__X >> (-__C & 31));
}

/* 8bit ror */
extern __inline unsigned char
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rorb (unsigned char __X, int __C)
{
  return __builtin_ia32_rorqi (__X, __C);
}

/* 16bit ror */
extern __inline unsigned short
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rorw (unsigned short __X, int __C)
{
  return __builtin_ia32_rorhi (__X, __C);
}

/* 32bit ror */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rord (unsigned int __X, int __C)
{
  __C &= 31;
  return (__X >> __C) | (__X << (-__C & 31));
}

/* Pause */
extern __inline void
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__pause (void)
{
  __builtin_ia32_pause ();
}

#ifdef __x86_64__
/* 64bit bsf */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bsfq (long long __X)
{
  return __builtin_ctzll (__X);
}

/* 64bit bsr */
extern __inline int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bsrq (long long __X)
{
  return __builtin_ia32_bsrdi (__X);
}

/* 64bit bswap */
extern __inline long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bswapq (long long __X)
{
  return __builtin_bswap64 (__X);
}

#ifndef __SSE4_2__
#pragma GCC push_options
#pragma GCC target("sse4.2")
#define __DISABLE_SSE4_2__
#endif /* __SSE4_2__ */

/* 64bit accumulate CRC32 (polynomial 0x11EDC6F41) value.  */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__crc32q (unsigned long long __C, unsigned long long __V)
{
  return __builtin_ia32_crc32di (__C, __V);
}

#ifdef __DISABLE_SSE4_2__
#undef __DISABLE_SSE4_2__
#pragma GCC pop_options
#endif /* __DISABLE_SSE4_2__ */

/* 64bit popcnt */
extern __inline long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__popcntq (unsigned long long __X)
{
  return __builtin_popcountll (__X);
}

/* 64bit rol */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rolq (unsigned long long __X, int __C)
{
  __C &= 63;
  return (__X << __C) | (__X >> (-__C & 63));
}

/* 64bit ror */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__rorq (unsigned long long __X, int __C)
{
  __C &= 63;
  return (__X >> __C) | (__X << (-__C & 63));
}

/* Read flags register */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__readeflags (void)
{
  return __builtin_ia32_readeflags_u64 ();
}

/* Write flags register */
extern __inline void
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__writeeflags (unsigned long long __X)
{
  __builtin_ia32_writeeflags_u64 (__X);
}

#define _bswap64(a)		__bswapq(a)
#define _popcnt64(a)		__popcntq(a)
#else

/* Read flags register */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__readeflags (void)
{
  return __builtin_ia32_readeflags_u32 ();
}

/* Write flags register */
extern __inline void
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__writeeflags (unsigned int __X)
{
  __builtin_ia32_writeeflags_u32 (__X);
}

#endif

/* On LP64 systems, longs are 64-bit.  Use the appropriate rotate
 * function.  */
#ifdef __LP64__
#define _lrotl(a,b)		__rolq((a), (b))
#define _lrotr(a,b)		__rorq((a), (b))
#else
#define _lrotl(a,b)		__rold((a), (b))
#define _lrotr(a,b)		__rord((a), (b))
#endif

#define _bit_scan_forward(a)	__bsfd(a)
#define _bit_scan_reverse(a)	__bsrd(a)
#define _bswap(a)		__bswapd(a)
#define _popcnt32(a)		__popcntd(a)
#ifndef __iamcu__
#define _rdpmc(a)		__rdpmc(a)
#define _rdtscp(a)		__rdtscp(a)
#endif /* __iamcu__ */
#define _rdtsc()		__rdtsc()
#define _rotwl(a,b)		__rolw((a), (b))
#define _rotwr(a,b)		__rorw((a), (b))
#define _rotl(a,b)		__rold((a), (b))
#define _rotr(a,b)		__rord((a), (b))